The present invention relates to a synchronous semiconductor memory device utilizing the latency technique, and more specifically to a data transfer system and data transfer method for transferring data through multiple data transfer stages under pipeline control.
Recently, there has been put into practical use semiconductor memory devices, such as synchronous dynamic random access memories (xe2x80x9cSDRAMsxe2x80x9d), in which data transfer control is simplified and high-speed data transfer is attained by synchronizing the control process with a clock signal. In the conventional SDRAM, a latency technique is used to enhance the clock frequency by masking (or apparently disregarding) the time required to output data from the memory cell to the exterior of the device. The latency indicates the minimum number of cycles required from the cycle in which an address is fetched to the cycle in which the data specified by the address is output. Such conventional SDRAMs are disclosed in Japanese Patent Application KOKAI Publication No. 5-2873 (corresponding to U.S. Pat. No. 5,313,437) and Japanese Patent Application KOKAI Publication No. 6-76563 (corresponding to U.S. Pat. No. 5,392,254).
FIG. 27 shows the relation between an external clock signal CLK and data output Dout in one case where the latency is xe2x80x9c4xe2x80x9d (LTC=4) and another case where the latency is xe2x80x9c1xe2x80x9d (LTC=1). If access is started at the rise of the clock at t0, the data transfer time T required for outputting the first data item of a series of data items is the same regardless of the latency because the data transfer time is determined by the characteristics of the memory device itself. If the latency is increased and the memory is controlled by a clock of constant period, more cycles are allotted to the data transfer time so that the clock period can be shortened and a high-frequency clock can be used to output the data. With a high-frequency clock, memory access and data transfer can be performed at a high speed in synchronism with the high-frequency clock, and the amount of data output per time unit can be increased, as can be understood from FIG. 27.
When the latency is xe2x80x9c1xe2x80x9d, the data transfer operation from the rise of the external clock signal CLK to the output of data can be performed as a sequence of operations. On the other hand, when the latency is xe2x80x9c4xe2x80x9d, a plurality of data items are present in the same data transfer path, so a method for simultaneously transferring the data items in one block or a pipeline method for transferring the data must be used. In the pipeline method, the data transfer path is divided into segments, the data items in the segments are simultaneously transferred to construct a pipeline stage, and then the data is shifted between segments in a time sharing fashion. Because it is not necessary to previously determine the data block in the pipeline method, the data to be transferred can be freely selected for each clock cycle. However, if the latency is changed when the pipeline method is being used to transfer the data, the following problem occurs.
When a memory device using the pipeline method an and having a latency of xe2x80x9c4xe2x80x9d is changed from a high-frequency clock to a low-frequency clock, the apparent data transfer time is made longer if the latency is not changed. But, if the latency is changed from xe2x80x9c4xe2x80x9d to xe2x80x9c1xe2x80x9d, the number of stages in the data transfer pipeline must be changed so as to complete the data transfer in the cycle of the latency. Thus, the number of stages in the pipeline must be changed for each change in the latency. However, in order to change the number of pipeline stages, drastic changes must be made in the circuit construction and operation timing of the memory device. Thus, for each latency to be selectively used, pipeline control and operation timing for that latency must be designed into the device, so the data transfer system and the semiconductor memory device become complicated. Furthermore, the system must be re-designed to allow a latency other than the latencies already designed into the device to be used, so it is extremely difficult to flexibly cope with various latency requirements.
As explained above, in the conventional synchronous memory device using the pipeline-type data transfer system, the number of pipeline stages must be changed each time the latency is changed, and this requires drastic changes in the circuit construction and operation timing of the device. Further, in the conventional synchronous memory device using the latency technique, in order to use a latency other than the latencies already designed into the device, the memory device must be re-designed so it is extremely difficult to provide a device that can flexibly satisfy various latency requirements.
In view of these problems, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a pipeline-type data transfer system and data transfer method in which the latency can be changed without changing the number of data transfer stages or the control of the individual data transfer stages, so that various latency requirements can be easily satisfied.
Another object of the present invention is to provide a synchronous semiconductor memory device that can easily cope with a latency other than the latencies previously taken into consideration so that various latency requirements can be flexibly satisfied, and a memory system using the synchronous semiconductor memory device.
To achieve this object, a first preferred embodiment of the present invention provides a data transfer system that includes a system having successive stages connected in series. Each of the stages performs a partial operation necessary for transferring data in synchronism with a control clock, and the system transfers data by sequentially operating the stages and performs pipeline control to allow two or more stages to simultaneously transfer data. Also included is a clock generating circuit for generating internal clock signals based on an external clock signal supplied to the system, and a clock switching circuit for selectively switching the external clock signal and the internal clock signals generated by the clock generating circuit to control the operation of each of the stages.
In one embodiment, the clock generating circuit generates the internal clock signals based on a latency of the system, with the latency indicating the number of external clock cycles from the start of data access to data output. Further, the clock generating circuit generates the internal clock signals by sequentially delaying the external clock signal.
In another embodiment, there is a first mode in which all of the stages are controlled by the external clock signal, and a second mode in which only a first stage of the successive stages is controlled by the external clock signal and the other stages are controlled by the internal clock signals generated by the clock generating circuit.
In yet another embodiment, there is a mode in which a first stage and at least one intermediate stage of the successive stages are controlled by the external clock signal, and the other stages are controlled by the internal clock signals generated by the clock generating circuit.
Because the clock generating circuit generates the internal clock signals based on the external clock signal and the clock switching circuit selectively switches the external clock signal and the internal clock signals to change the clock signals that control the stages so as to change the latency, it becomes possible to easily cope with a change in the latency without having to change the number of data transfer segments or the control of the individual data transfer stages. Additionally, if the internal clock signals are generated based on the latency of the system, it becomes possible to easily generate the internal clock signals corresponding to that latency. And if the internal clock signals are generated by sequentially delaying the external clock signal, it becomes possible to more easily generate the internal clock signals and to prevent the internal clock signals from overlapping each other. Further, if all of the stages are controlled by the external clock signal, a latency which is equal to the number of stages is obtained, and if only the first stage is controlled by the external clock signal and the other stages are controlled by the internal clock signals, the latency becomes xe2x80x9c1xe2x80x9d.
According to a second preferred embodiment of the present invention, a data transfer system is provided that includes a system having a plurality of successive stages connected in series. Each of the stages performs a partial operation necessary for transferring data in synchronism with a control clock, the system transfers data by sequentially operating the stages and performs pipeline control to allow two or more stages to simultaneously transfer data, and each stage transfers one data item at a time or simultaneously transfers two or more data items at a time as a block of data. Also provided is a clock generating circuit that generates internal clock signals based on an external clock signal and a series of paths, and supplies the internal clock signals to the system to control the operation of the stages, and path switching circuit that selectively switches the paths of the clock generating circuit so that the internal clock signals are generated in response to an external control signal.
In one embodiment the paths of the clock generating circuit are selected based on a selected latency for the system, with the latency indicating the number of external clock cycles from the start of data access to data output. Additionally, the clock generating circuit generates one internal clock signal from the external clock signal based on the number of stages and the number of data items to be transferred at a time, and generates a plurality of other internal clock signals based on the one internal clock via the series of paths.
In the second preferred embodiment, the internal clock signals can be generated based on the external clock signal by the clock generating circuit, and the external clock signal and the internal clock signals can be selectively switched as a control signal supplied to each stage of the system by the clock switching circuit. Therefore, it becomes possible to provide a pipeline-type data transfer system that can easily cope with a change of latency, without having to change the number of data transfer segments or the control of the individual data transfer stages. Additionally, the internal clock signals corresponding to the selected latency can be easily generated by selecting paths for generating the internal clock signals based on the selected latency. Further, if one internal clock is generated and then a plurality of internal clock signals are generated based on the one internal clock via a series of paths, a plurality of internal clock signals can be easily generated.
A third preferred embodiment of the present invention provides a data transfer method in which internal clock signals are generated based on an external clock signal that is supplied to a system having a plurality of successive stages connected in series, with each of the stages performing a partial operation necessary for transferring data in synchronism with a control clock. The external clock signal and the internal clock signals are selectively supplied to the successive stages to transfer data by sequentially operating the stages and to perform pipeline control to allow two or more of the stages to simultaneously transfer data, and the number of pipeline stages is changed by selectively changing the timings of at least one of the external clock signal and the internal clock signals that control the operation of the stages.
In one embodiment, the internal clock signals are generated based on a selected latency for the system, with the latency indicating the number of external clock cycles from the start of data access to data output. Further, the internal clock signals are generated by sequentially delaying the external clock signal.
Another embodiment provides a first mode in which all of the successive stages are controlled by the external clock signal, and a second mode in which only a first stage of the successive stages is controlled by the external clock signal and the other stages are controlled by the internal clock signals.
Yet another embodiment provides a mode in which a first stage and at least one intermediate stage of the successive stages are controlled by the external clock signal, and the other stages are controlled by the internal clock signals.
Because the number of pipeline stages is changed by generating internal clock signals based on the external clock signal and selectively switching the external clock signal and the internal clock signals to control the operation of each stage, it is possible to provide a pipeline-type data transfer method that can easily cope with a change of latency, without having to change the number of data transfer segments or the control of the individual data transfer stages. Additionally, if the internal clock signals are generated based on the external clock signal according to the selected latency, the internal clock signals corresponding to the selected latency can be easily generated. And if the internal clock signals are generated by sequentially delaying the external clock signal, the internal clock signals corresponding to the selected latency can be more easily generated and prevented from overlapping each other. Further, if all of the stages are controlled by the external clock signal, a latency equal to the number of pipeline stages is obtained, and if only the first stage is controlled by the external clock signal and the other stages are controlled by the internal clock signals, the latency becomes xe2x80x9c1xe2x80x9d.
A fourth preferred embodiment of the present invention provides a data transfer method in which internal clock signals are generated based on an external clock signal which is supplied to a system having a plurality of successive stages connected in series, with each of the stages performing a partial operation necessary for transferring data in synchronism with a control clock. The internal clock signals are selectively supplied to the successive stages to transfer data by sequentially operating the stages and to perform pipeline control to allow two or more of the stages to simultaneously transfer data, with each stage transferring one data item at a time or simultaneously transferring two or more data items at a time as a block of data. Additionally, the number of pipeline stages is changed by selectively changing the timings of the internal clock signals in response to an external control signal.
In one embodiment, the internal clock signals are generated based on a selected latency, with the latency indicating the number of external clock cycles from the start of data access to data output. Additionally, one internal clock signal is generated from the external clock signal based on the number of stages and the number of data items to be transferred at one time, and a plurality of other internal clock signals are generated based on the one internal clock signal.
In the fourth preferred embodiment, the internal clock signals can be generated based on the external clock signal and the internal clock signals can be selectively switched in response to a control signal. Therefore, it is possible to provide a pipeline-type data transfer method that can easily cope with a change of latency without having to change the number of data transfer segments or the control of the individual data transfer stages. Additionally, if the internal clock signals are generated based on the selected latency, the internal clock signals corresponding to the selected latency can be easily generated. And if one internal clock is generated according to the external clock signal and then a plurality of internal clock signals are generated based on the one internal clock, the internal clock signals corresponding to the selected latency can be more easily generated.
A fifth preferred embodiment of the present invention provides a semiconductor memory device that includes four stages, a controller, and a switching circuit. The first stage includes an address generating circuit that fetches a top address of a data burst and generates a sequence of addresses based on the top address, and a column decoder that decodes the address generated by the address generating circuit and generates a selection signal for a sense amplifier. The second stage latches the selection signal and couples the selected sense amplifier to a data transfer line to transfer data. The third stage includes a DQ buffer that senses and latches the data transferred to the data transfer line, with the data latched by the DQ buffer being supplied to an output driver. The fourth stage latches the data supplied to the output driver and outputs the data to the exterior of the memory device. The controller includes a clock generating circuit that generates internal clock signals based on an external clock signal, with the external clock signal and internal clock signals being selectively supplied to the first to fourth stages to control the stages in a pipeline fashion. Additionally, the switching circuit changes the number of pipeline stages by selectively switching the external clock signal and the internal clock signals to change the operation of the stages.
In one embodiment, the clock generating circuit generates the internal clock signals from the external clock signal based on a selected latency for the device by sequentially delaying the external clock signal.
In the fifth preferred embodiment, the number of pipeline stages can be switched according to the selected latency by controlling the first to fourth stages in a pipeline fashion by use of the controller and selectively switching the external clock signal and the internal clock signals to change the operation of the stages. Therefore, it is possible to provide a synchronous-type semiconductor memory device that can cope with a latency other than the latencies previously taken into consideration to flexibly cope with various latency requirements. Further, if the internal clock signals are generated based on the selected latency, the internal clock signals corresponding to the selected latency can be easily generated. And if the internal clock signals are generated by sequentially delaying the external clock signal, the internal clock signals corresponding to the selected latency can be more easily generated and prevented from overlapping each other.
A sixth preferred embodiment of the present invention provides a semiconductor memory device that includes four stages, a controller, and a switching circuit. The first stage includes an address generating circuit that fetches a top address of a data burst and generates a sequence of addresses based on the top address, and a column decoder that decodes the address generated by the address generating circuit and generates a selection signal for a sense amplifier. The second stage latches the selection signal and couples the selected sense amplifier to a data transfer line to transfer data, and the third stage includes a DQ buffer that senses and latches the data transferred to the data transfer line. The data latched by the DQ buffer is supplied to an output driver, and the fourth stage latches the data supplied to the output driver and outputs the data to the exterior of the memory device. The controller includes a clock generating circuit that generates internal clock signals based on an external clock signal and a series of paths, with the internal clock signals being selectively supplied to the first to fourth stages to control the stages in a pipeline fashion. Additionally, the switching circuit changes the number of pipeline stages by selectively switching the paths of the clock generating circuit in response to an external control signal to change the operation of the stages.
In one embodiment, the external control signal defines a selected latency for the device, and the paths of the clock generating circuit are switched based on the selected latency. Further, the clock generating circuit generates one internal clock signal from the external clock signal based on the number of stages and the number of data items to be transferred at one time, and generates a plurality of other internal clock signals based on the one internal clock signal via the series of paths.
In the sixth preferred embodiment, the internal clock signals can be selectively supplied to the first to fourth stages to control the stages in a pipeline fashion, and the paths for generating the internal clock signals can be selectively switched in response to a control signal that corresponds to the selected latency to change the operation of the stages. Therefore, it is possible to provide a clock synchronous type semiconductor memory device which can cope with a latency other than the latencies previously taken into consideration to flexibly cope with various latency requirements. Further, if the internal clock signals are generated based on the selected latency, the internal clock signals corresponding to the selected latency can be easily generated. And if one internal clock is generated according to the external clock signal and then a plurality of internal clock signals are generated based on the one internal clock, the internal clock signals corresponding to the latency can be more easily generated.
A seventh preferred embodiment of the present invention provides a memory system having a memory chip, a CPU that supplies a clock signal to the memory chip and controls data readout and data writing with respect to the memory chip, and a bus that allows data to be transferred between the memory chip and the CPU. The memory chip includes control means having a plurality of successive stages connected in series, with each of the stages performing a partial operation necessary for transferring data in synchronism with a control clock. The control means transfers data by sequentially operating the stages and performs pipeline control to allow two or more stages to simultaneously transfer data. Also included is a clock generating circuit that generates internal clock signals based on the clock signal supplied by the CPU, and a clock switching circuit that selectively switches the clock signal supplied by the CPU and the internal clock signals generated by the clock generating circuit to control the operation of each of the stages.
Because the clock signals for controlling the stages can be changed to change the latency by generating the internal clock signals based on the clock supplied by the CPU using the clock generating circuit and selectively switching the clock supplied from the CPU and the internal clock signals using the clock switching circuit, it is possible to construct a memory system that can easily cope with a change of latency without having to change the number of data transfer segments or the control of the individual data transfer stages.
An eighth preferred embodiment of the present invention provides a memory system having a memory chip, a CPU that supplies a clock signal to the memory chip and controls data readout and data writing with respect to the memory chip, and a bus that allows data to be transferred between the memory chip and the CPU. The memory chip includes control means having a plurality of successive stages connected in series, with each of the stages performing a partial operation necessary for transferring data in synchronism with a control clock. The control means transfers data by sequentially operating the stages and performs pipeline control to allow two or more stages to simultaneously transfer data, with each stage transferring one data item at a time or simultaneously transferring two or more data items at a time as a block of data. Also included is a clock generating circuit that generates internal clock signals based on the clock signal supplied by the CPU and a series of paths and supplies the internal clock signals to the control means to control the operation of the stages, and a path switching circuit that selectively switches the paths of the clock generating circuit in response to the control signal supplied by the CPU.
According to the eighth preferred embodiment, the internal clock signals can be generated based on the clock supplied by the CPU using the clock generating circuit, and the clock supplied by the CPU and the internal clock signals can be selectively switched as control clocks for the stages of the system using the clock switching circuit. Therefore, it is possible to construct a memory system that can easily cope with a change of latency without having to change the number of data transfer segments or the control of the individual data transfer stages.
A ninth preferred embodiment of the present invention provides a memory system having a memory chip, a CPU that supplies a clock signal to the memory chip and controls data readout and data writing with respect to the memory chip, and a bus that allows data to be transferred between the memory chip and the CPU. The memory chip includes a first stage having an address generating circuit that fetches a top address of a data burst and generates a sequence of addresses based on the top address, and a column decoder that decodes the address generated by the address generating circuit and generates a selection signal for a sense amplifier, a second stage that latches the selection signal and couples the selected sense amplifier to a data transfer line to transfer data, a third stage including a DQ buffer that senses and latches the data transferred to the data transfer line, and a fourth stage that latches the data from the DQ buffer and outputs the data to the exterior of the chip. Also included is control means including a clock generating circuit for generating internal clock signals based on the clock signal supplied by the CPU, with the clock signal supplied by the CPU and the internal clock signals being selectively supplied to the first to fourth stages to control the stages in a pipeline fashion. A switching circuit changes the number of pipeline stages based on a selected latency by selectively switching the clock signal supplied by the CPU and the internal clock signals to change the operation of the stages.
According to the ninth preferred embodiment, the number of pipeline stages can be switched according to the selected latency by controlling the first to fourth stages in a pipeline fashion using the control circuit and selectively switching the clock supplied by the CPU and the internal clock signals to change the operations of the stages. Therefore, it is possible to provide a memory system which can easily cope with a latency other than the latencies previously taken into consideration to flexibly cope with various latency requirements.
A tenth preferred embodiment of the present invention provides a memory system having a memory chip, a CPU that supplies a clock signal to the memory chip and controls data readout and data writing with respect to the memory chip, and a bus that allows data to be transferred between the memory chip and the CPU. The memory chip includes a first stage having an address generating circuit that fetches a top address of a data burst and generates a sequence of addresses based on the top address and a column decoder that decodes the address generated by the address generating circuit and generates a selection signal for a sense amplifier, a second stage that latches the selection signal and couples the selected sense amplifier to a data transfer line to transfer data, a third stage including a DQ buffer that senses and latches the data transferred to the data transfer line, and a fourth stage that latches the data from the DQ buffer and outputs the data to the exterior of the chip. Also included is control means including a clock generating circuit that generates internal clock signals based on the clock supplied by the CPU and a series of paths, with the internal clock signals being selectively supplied to the first to fourth stages to control the stages in a pipeline fashion. A switching circuit changes the number of pipeline stages based on the control signal supplied by the CPU by selectively switching the paths of the clock generating circuit to change the operation of the stages.
In the tenth preferred embodiment, the internal clock signals can be selectively supplied to the first to fourth stages to control the stages in a pipeline fashion, and the paths for generating the internal clock signals can be selectively switched in response to a control signal supplied by the CPU to change the operation of each of the stages. Therefore, it is possible to provide a memory system which can cope with a latency other than the latencies previously taken into consideration to flexibly cope with various latency requirements.
Some embodiments of the memory system of the present invention also include at least one electronic device that receives data read out from the memory chip and is controlled based on the received data, and a controller that supplies an address to the memory chip via the bus. In these embodiments, the electronic device can be controlled according to data stored in the memory chip under the control of the CPU by supplying data read out from the memory chip to the electronic device via the bus. Further, the address to the memory chip can be supplied not only by the CPU, but also by the controller.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the scope of the present invention.